AERIS-10 is a rare open-source implementation of a full 10.5 GHz X-band phased array radar system, built with low-cost components and complete FPGA-based real-time signal processing. This project makes advanced radar engineering accessible beyond defense contractors by providing all hardware designs, FPGA logic, firmware, and a Python GUI under open licenses.
What AERIS-10 radar system includes
The AERIS-10 project is actually two radar configurations sharing the same core design: the AERIS-10N (Nexus) and the AERIS-10X (Extended). Both operate at 10.5 GHz (X-band) and use phased array antennas combined with Pulse Linear Frequency Modulation (LFM) for radar signal transmission.
The AERIS-10N features an 8×16 patch antenna array with about 1 W output power per channel, reaching up to 3 km range. The AERIS-10X uses a larger 32×16 dielectric-filled slotted waveguide antenna array powered by 10 W GaN amplifiers per channel, extending range up to 20 km.
Under the hood, a Xilinx XC7A100T FPGA handles the entire real-time signal processing pipeline including pulse compression, Doppler FFT, Moving Target Indication (MTI), and Constant False Alarm Rate (CFAR) detection algorithms. This FPGA offloads the heavy digital signal processing that radar requires to detect and track targets.
The system uses an STM32F746 microcontroller to manage auxiliary functions: power sequencing, peripheral control, GPS and IMU integration, and mechanical stepper motor control for 360° scanning.
Electronic beam steering is achieved with ±45° range in both elevation and azimuth using phased array beamforming, combined with 360° mechanical rotation for full coverage.
All hardware schematics, PCB layouts, FPGA IP cores, firmware source code, and the Python GUI are published openly. This provides an end-to-end open-source radar stack that can be built and experimented with by advanced hobbyists, researchers, or small teams.
Technical strengths and design tradeoffs
One standout technical strength is the full FPGA-based real-time signal processing pipeline. Implementing pulse compression and Doppler processing on the Xilinx FPGA reduces latency and offloads the embedded microcontroller. This is critical for radar where fast, continuous processing of reflected pulses is required.
The use of Pulse Linear Frequency Modulation (LFM) pulses improves range resolution and detection sensitivity compared to simple pulse radar.
The phased array antenna design combined with electronic beam steering enables rapid directional scanning without mechanical repositioning alone. The ±45° electronic steering range allows agile scanning in two dimensions, while the 360° mechanical rotation covers the full azimuth.
The hardware design leverages relatively affordable components such as ADAR1000/ADTR1107 RF front-end ICs and GaN power amplifiers, balancing cost and performance.
From an engineering perspective, the project requires significant expertise in PCB assembly and FPGA development. The assembly process involves ordering and populating PCBs with surface mount components, which can be challenging without experience or professional tools.
FPGA development uses Xilinx Vivado tools, which have a steep learning curve and require a licensed environment. Modifying or extending the signal processing pipeline is not trivial.
The Python GUI requires Python 3.8+ and serves as the user interface for radar control and data visualization. This separation between embedded firmware and the GUI provides flexibility but means multiple environments must be managed.
Getting started with AERIS-10
The project README provides a clear roadmap for assembling and running the system.
Hardware assembly steps include:
# 1. Order PCBs from Gerber files in /4_Schematics and Boards Layout
# 2. Source components using the BOM in /4_Schematics and Boards Layout/4_7_Production Files
# 3. Follow the assembly guide in /10_docs/assembly_guide.md
# 4. Choose the antenna array version (Nexus or Extended)
# 5. Use 3D printable enclosure files in /10_docs/Hardware/Enclosure
Software prerequisites:
- Python 3.8 or newer for the GUI
- Xilinx Vivado FPGA tools for any FPGA signal processing work
The STM32F746 microcontroller firmware and FPGA bitstreams are included in the repo. Users can load these onto the hardware after assembly.
The Python GUI allows controlling the radar parameters, viewing processed radar data, and managing scans.
Verdict
AERIS-10 is a comprehensive open-source phased array radar project that delivers a complete hardware and software stack. The open FPGA signal processing pipeline and the detailed hardware documentation set it apart from typical radar projects that remain proprietary.
That said, this is a project for experienced engineers comfortable with embedded hardware assembly, FPGA development, and RF design. The learning curve is steep, and the hardware complexity is non-trivial.
For researchers, educators, or advanced hobbyists interested in radar systems, this repo is a rare resource to study and build a real phased array radar system from scratch.
If you lack hardware assembly experience or FPGA tooling, the barrier to entry will be high. But for those who clear it, the project offers a deep dive into radar engineering with fully open designs and code.
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→ GitHub Repo: mitgor/PLFM_RADAR ⭐ 357 · C