Digital is a digital logic simulator and circuit design tool written in Java that tackles a core problem with one of the most popular educational simulators: Logisim. The key difference is its event-based simulation model combined with a novel “switching on” settling phase, which solves the unstable flip-flop states and inconsistent circuit behaviors that Logisim’s architecture can produce after resets or circuit modifications. This foundational fix makes Digital a more reliable choice for both teaching and prototyping complex digital circuits.
What Digital does and how it’s built
Digital is a Java application designed from the ground up as an alternative to Logisim, aiming to offer more accurate and stable circuit simulation. It models digital circuits as networks of interconnected components that communicate via discrete events rather than continuous polling or level-triggered updates.
The architecture revolves around an event-driven simulation engine that processes signal changes asynchronously and propagates them through the circuit. This contrasts with Logisim’s approach, which can suffer from race conditions and unstable states due to its update algorithm. Digital introduces a “switching on” settling phase at startup or after circuit changes, ensuring that signals settle into a stable state before further simulation proceeds.
The simulator supports key features beyond basic logic gates: it can simulate components described in VHDL and Verilog, export circuits for FPGA boards like BASYS3 and TinyFPGA BX, and generate JEDEC files for GAL programmable logic chips. It also exposes a remote TCP interface that allows integration with IDEs or external tools, enhancing its extensibility.
From a technology stack perspective, Digital is written purely in Java, which makes it cross-platform and easy to run wherever a suitable Java Runtime Environment is available. The project maintains solid test coverage (~80%) for core logic, although GUI and HDL integration tests are partially excluded from CI runs.
Why Digital’s event-driven simulation stands out
The distinguishing technical strength of Digital is its event-based simulation combined with the “switching on” settling phase. This addresses a notorious problem in Logisim: circuits with feedback loops and stateful elements like flip-flops can end up in unstable or inconsistent states after resets or edits. Logisim’s simulation sometimes leaves these components in undefined or oscillating conditions because it doesn’t have a proper initialization sequence or stable state convergence mechanism.
Digital’s approach schedules discrete events representing signal changes and processes them asynchronously. The “switching on” phase is a key innovation — it iteratively settles the circuit by repeatedly propagating signal changes until no further transitions occur, guaranteeing a stable starting point before the user interacts with the design.
This technique is reminiscent of event-driven simulation models used in professional EDA tools but adapted here to an educational and lightweight Java-based environment. It trades off some simulation speed and simplicity in favor of correctness and stability. As a result, Digital can reliably simulate complex circuits, including an example processor running at 120 kHz and a “Conway’s Game of Life” circuit with around 2400 components.
The codebase is surprisingly clean for a project of this scope. The event queue and signal propagation logic are well encapsulated, and the design favors extendability — for example, adding support for new FPGA targets or HDL components is straightforward. The project also includes a remote TCP interface, which is a thoughtful addition for embedding the simulator into larger workflows or IDE environments.
The tradeoff here is complexity: event-driven simulation is inherently more complex than level-based approaches, and this can translate into a steeper learning curve for contributors or users who want to extend the tool. Also, GUI tests and some HDL integration tests are not fully automated in CI, which means some edge cases might slip through unnoticed. Still, 80% coverage on core logic is respectable.
Quick start
There is no installation required for Digital. You just need to download and unpack the Digital.zip file available from the project’s releases. Running the software requires at least Java Runtime Environment 8.
On Linux, start the provided shell script. On Windows and MacOS, you can directly launch the JAR file. If you encounter startup problems, try running the following command from the Digital folder:
java -jar Digital.jar
This simplicity makes Digital very accessible for quick experimentation without complex environment setup.
Verdict
Digital is a solid choice for anyone interested in digital logic design who has struggled with the quirks of Logisim’s simulation instability. Its event-driven simulation model with a “switching on” settling phase fixes fundamental circuit stability issues, making it reliable for both educational use and moderate-scale prototyping.
Its support for VHDL/Verilog components and FPGA export targets adds practical value beyond a pure teaching tool. The Java implementation ensures cross-platform compatibility and ease of use.
The main limitations are the increased complexity under the hood and the partial test coverage on GUI and integration fronts, which means users extending the tool should prepare for some manual testing and debugging.
Overall, Digital is worth exploring if you want a more dependable and extensible digital logic simulator that stays true to the educational spirit but handles real-world circuit edge cases better than many alternatives.
→ GitHub Repo: hneemann/Digital ⭐ 5,690 · Java